1. Field of the invention
The present invention relates to a microcomputer system comprising a microcomputer as a semiconductor device integrated on a single chip, namely a single-chip microcomputer, and an external memory externally connected thereto, and particularly to address allocation of a read only memory (ROM) thereto.
2. Description of the Related Art
An example of configuration of a conventional microcomputer system using a single-chip microcomputer as a core and allocation of the address space thereof will be described below with reference to FIG. 1 through FIG. 5.
At first, internal configuration of a general single-chip microcomputer of the prior art and an example of configuration of external devices connected externally to the single-chip microcomputer will be described with reference to a block diagram of FIG. 1.
In FIG. 1, reference numeral 20 denotes the single-chip microcomputer (hereinafter, referred to simply as a microcomputer) which is constituted as an integrated circuit built on a single chip.
Provided inside the microcomputer 20, namely on the chip, are a central processing unit (hereinafter abbreviated as a CPU) 21, internal resources such as an internal ROM 22, an internal RAM 23 and the like, a mode set register 24, a control register 28, an input/output control unit (I/O) 30, a bus interface unit (bus I/F) 27 and others, that are connected with each other via an internal address bus 25 and an internal data bus 26.
The CPU 21 controls the microcomputer 20 as a whole and external devices to be described later, and carries out various operations.
The bus I/F 27 handles data exchanging between the microcomputer 20 and the outside thereof, and is connected to an external ROM 32, an external RAM 33, an exclusive IC 34 and other devices which are provided outside the microcomputer 20 and connected thereto via an external address bus 250 and an external data bus 260.
Reference numeral 29 denotes a peripheral device which is controlled by the CPU 21 through writing control data into the control register 28. Reference numeral 31 denotes a port group used in exchanging signals with the outside via the I/O 30.
FIG. 2 is a block diagram showing more specific configuration of the internal ROM 22.
In FIG. 2, reference numeral 36 denotes the body (internal ROM body) of the internal ROM 22, namely memory elements, and reference numeral 35 denotes an address decoder.
The address decoder 35 receives address signal AD0-ADn outputted from the CPU 21 via the internal address bus 25. When the CPU 21 outputs an address signal, the address decoder 35 decodes it and gives the decoded signal 41 to the internal ROM body 36, and the internal ROM body 36 outputs data stored at the corresponding address onto the internal data bus 26 as data signal DO-Dm.
Reference numeral 42 denotes an internal ROM area select signal which becomes in ineffective when an address allocated to the internal ROM 22 is outputted from the CPU 21, and thereby activates the internal RAM 23.
FIG. 3 is a schematic diagram showing an address allocation under an extended memory mode in the conventional microcomputer system. The extended memory mode is a mode where the external resources such as the external ROM 32, the external RAM 33, the exclusive IC 34 and the like that are connected to the microcomputer 20 externally are used in addition to the internal resources provided on the chip such as the internal ROM 22, the internal RAM 23, the control register 28 and the like. Single-chip mode, on the other hand, is a mode where only the above-mentioned internal resources provided on the chip are used.
In FIG. 3, an area indicated by reference numeral 1 shows an SFR (Special Function Register) area. The SFR area 1 ranges from address "0000H" (H indicates that, the number is hexadecimal) to "007FH", each address being allocated to the control register 28 or other element.
An area indicated by reference numeral 2 shows an internal RAM area of the conventional microcomputer system. The internal RAM area 2 ranges from address "0080H" to "0086H", to which addresses of the internal RAM 23 are allocated.
An area indicated by reference numeral 4 shows an interrupt vector area. The interrupt vector area 4 ranges from address "E000H" to "FFFFH", in which the addresses of jump destination addresses of interrupt handlers to be executed at generation of interrupt are stored.
An area indicated by reference numeral 37 shows an area other than the SFR area 1, the internal RAM area 2 and the interrupt vector area 4 described above. The area 37 is an area which can be used as an internal ROM area, namely an area whereto the addresses of the internal ROM 22 can be allocated.
FIG. 4 is a schematic diagram of an address allocation of FIG. 3 described above, wherein an area 39, which includes an area of 32K bytes from address "8000H" to "DFFFH" in the area 37 that can be used as the internal ROM area and the interrupt vector area 4, is allocated to the internal ROM area, while an area 38 of the remaining addresses from "0087H" to "7FFFH" is left reserved.
FIG. 5 is a schematic diagram of an address allocation of FIG. 3 described above, wherein an area 40, which includes an area of 60K bytes from address "1000H" to "DFFFH" in the area 37 that can be used as the internal ROM area and the interrupt vector area 4, is allocated to the internal ROM area, while the area 38 of the remaining addresses from "0087H" to "0FFFH" is left reserved.
In the conventional microcomputer system, under a mode other than the single-chip mode under which only the internal resources such as the internal ROM 22, the internal RAM 23 and the like are used, external resources such as the external ROM 32, the external RAM 33 and the like are connected as shown in FIG. 1, and such an address allocation as shown in FIG. 3 is basically employed. And the external memory is allocated to the portion remaining after allocating the internal ROM area to the area 37.
In the case shown in FIG. 4, for example, access to the internal ROM 22 by the CPU 21 is carried out by outputting an optional address within the range from the address "8000H" to "FFFFH" shown in FIG. 4 onto the internal address bus 25. This makes the internal ROM area select signal 42 be effective. At the same time, the address outputted from the CPU 21 is inputted to the address decoder 35 shown in FIG. 2 and decoded, so that the decoded signal 41 in order to access to the internal ROM 22 is outputted. With the decoded signal 41 given, the internal ROM body 36 outputs data stored in the corresponding address onto the internal data bus 26.
In the case shown in FIG. 4, on the other hand, access to the external resources, particularly to the external ROM 32 and the external RAM 33, is made by the CPU 21 by outputting the address via the bus I/F 27 to the external address bus 250 and given to the external RAM 33. This causes the external RAM 33 to store the data outputted onto the external data bus 260 via the bus I/F 27 in the corresponding address, or to output the data from the corresponding address onto the external data bus 260.
The internal ROM area of the conventional microcomputer system is allocated within the area 37 that can be used as the internal ROM as indicated by reference numeral 39 in FIG. 4. As for the other portions that remain, external memories (ROM, RAM) or the like are allocated as the reserved area 38. In the conventional microcomputer, a memory sector of 64K bytes from address "0000H" to "FFFFH" (this sector of 64K bytes will be called a bank hereafter) is handled as a unit, and 256 banks from bank 0 to a bank 255 are prepared.
Shown in FIG. 3, FIG. 4 and FIG. 5 is bank 0. The internal ROM area 39 of 32K bytes and the internal ROM area of 60K bytes are all fixedly allocated in bank 0.
When 32K bytes of memory is allocated for the internal ROM area as shown in FIG. 4, an area from address "8000H" to "FFFFH" is used as the internal ROM area 39, and an area from address "0087H" to "7FFFH" becomes the reserved area 38 which is allocated for the external memory. Therefore, when RAM is used as the external memory, the RAM area which combines the internal and external areas becomes about 31K bytes of memory space from address "0080H" to "8000H".
Recently, however, microcomputer systems are in the trend of increasing storage capacity of the internal ROM 22 thereby causing the internal ROM area 39 to increase. When the internal ROM area 39 of FIG. 3 increases to 60K bytes, for example, the internal ROM area occupies from address "1000H" to "FFFFH" and the reserved area 38 occupies from address "0087H" to "1000H" as indicated by reference numeral 40 in FIG. 5. In the case of the example shown in FIG. 5, when RAM is used as the external memory similarly to the case described above it causes to the RAM area combining the internal and external areas to become as small as, or less than, about 4K bytes from address "0080H" to "0FFFH". The RAM area less than about 4K bytes is insufficient when temporary storage or saving of a large amount of data is required by a program.
The reason for employing such an address allocation, that all the memory areas for the internal ROM 22, the internal RAM 23 and the SFR are allocated in bank 0, is that this makes it easier to make a program under the single chip mode where the external memory is not used.
Thus when it is attempted to apply the address space of the conventional single-chip microcomputer just in this form to a microcomputer system comprising a single-chip microcomputer and an external memory, various problems arise. For this reason, it is desirable to employ such an arrangement that the address space allocation can be changed over depending on whether the single-chip microcomputer operates independently, namely under the single chip mode, or operates with the external memory connected thereto, namely under the extended memory mode. On the part of the manufacturer, because a single-chip microcomputer may be shipped as a complete product or shipped in a system after connecting the external memory thereto, it is desirable that either case can be easily provided for.